A digital bus provides circuits and a transmission medium for exchanging information between digital systems. A digital bus typically couples two or more systems that communicate using clocked data. Clocked data is data that is accompanied by a clock signal. The clock signal defines a time when the clocked data is valid. In one example system, a first processor controlling a data storage device, such as a disk drive, communicates with a second processor, such as a central processing unit (CPU), by sending and receiving information over a digital bus. In another example system, a CPU communicates with a memory, such as a solid state memory, by sending information to the memory and receiving information from the memory over a digital bus. The memory may be located on a die that includes the processor or located on a die that is separate from the processor.
Increasing the width of a bus connecting two digital systems generally increases the bandwidth of the bus. For example, early microprocessors typically transmitted and received information on four-bit and eight-bit buses, and generally supported only low bandwidth applications. Today, it is common to transmit information in digital systems on sixty-four bit buses, 128 bit buses, and 256 bit buses, all of which support high bandwidth applications. To reduce transmission errors, wide buses are subdivided into signaling groups. A signaling group typically comprises a plurality of data or information bits and an accompanying strobe or clock signal. A transition on the strobe or clock signal indicates that the accompanying data in the signaling group is valid. Unfortunately, because of manufacturing and electrical variations, such as strobe or clock transmission paths having different parasitic capacitances and strobe or clock driver and receiver circuits having different delays in different strobe and clock paths, the strobe or clock signal for each of the signaling groups on a bus may not arrive at a common receiving system at the same time. When strobe or clock information arriving at a receiving system are not synchronized, the receiving system cannot efficiently process the received data. One solution to this problem of skewed strobe or clock signals is to design the receiving system on the digital bus for the worst case arrival times of the strobes. Unfortunately, designing a bus for the worst case arrival times decreases the overall bandwidth of the system. Another solution to this problem of skewed strobe or clock signals is to synchronize a clock at the receiving system to the transmission clocks. Unfortunately, it is difficult to design a circuit that synchronizes a clock to multiple out-of-phase clocks or strobes without significantly reducing the bandwidth of the digital bus.
For these and other reasons there is a need for the present invention.